1. Luminance (S-video Y)
2. GND
3. Sound out
4. Composite videos
5. Audio in (max 3 Volts)
6. Chroma (S-video C)
7. NC
8. +5V (NC in early versions)
1. GND
2. GND
3. Red (RGB)
4. Green (RGB)
5. Blue (RGB)
6. Intensity
7. Monochrome
8. Horizontal sync
9. Vertical Sync
1. _SRQ
2. GND
3. ATN (Attention)
4. Clock
5. Date
6. _Reset
1 | GND | |
2 | + 5V | +5V (100mA max) |
3 | /RESET | Reset, also used to reset the connected device |
4 | CNT1 | Counter1, CIA #1 |
5 | SP1 | Serial port 1, CIA #1 |
6 | CNT2 | Counter 2, CIA #2 |
7 | SP2 | Serial port 2, CIA #2 |
8 | /PC2 | Handshaking, CIA #2 |
9 | AT extension | Serial attention in |
10 | 9VAC | 9VAC (100mA max) |
11 | 9VAC | 9VAC (100mA max) |
12 | GND |
TO | GND | |
b | /FLAG2 | Flags 2 |
c | PB0 | Date 0 |
D. | PB1 | Date 1 |
And | PB2 | Date 2 |
F. | PB3 | Date 3 |
H. | PB4 | Date 4 |
j | PB5 | Date 5 |
k | PB6 | Date 6 |
L | PB7 | Date 7 |
m | PA2 | PA2 |
No | GND |
1 | GND | |
2 | + 5V | +5V (100mA max) |
3 | /RESET | Reset, also used to reset the connected device |
4 | P2 | Date 2 |
5 | P3 | Date 3 |
6 | P4 | Date 4 |
7 | P5 | Date 5 |
8 | RCLK extension | Clock reception |
9 | AT extension | Serial attention in |
10 | 9VAC | 9VAC (100mA max) |
11 | 9VAC | 9VAC (100mA max) |
12 | GND |
TO | GND | |
b | P0 | Date 0 |
c | RXD extension | RX date |
D. | Rt0 | Request t0 send |
And | DTR extension | Data Terminal Ready |
F. | P7 | Date 7 |
H. | DCD extension | Data Carrier Detect |
j | P6 | Date 6 |
k | P1 | Date 1 |
L | dsr extension | Dataset ready |
m | TX extension | TX date |
No | GND |
1 | GND | |
2 | VIDEO | |
3 | /SRQ IN | |
4 | /EOI | Date 2 |
5 | DIAG | Date 3 |
6 | #2 CAS RD | Cassette reading #2 |
7 | CASWR | Cassette writing |
8 | #1 CAS RD | Cassette reading #1 |
9 | VDRIVE | Vertical drive |
10 | HDRIVE | Horizontal drive |
11 | GRAPHICS | 9VAC (100mA max) |
12 | GND |
TO | GND | |
b | CA1 | |
c | PA0 | Date 0 |
D. | PA1 | Date 1 |
And | PA2 | Date 2 |
F. | PA3 | Date 3 |
H. | PA4 | Date 4 |
j | PA5 | Date 5 |
k | PA6 | Date 6 |
L | V7 | |
m | CB2 | |
No | GND |
1. GND / NC
2. GND (black)
3. GND / NC
4. NC (On VIC20: +5V or NC)
5. +5V (red)
6. 9V ~ (Brown)
7. 9V ~ (white)
1. +5V (red)
2. GND (black)
3. 9V ~ (Brown)
4. 9V ~ (white)
1. +5V (1A)
2. GND
3. 9V ~ (0.75A)
4. 9V~
Internal: GND
External: +9V (0.8A)
PIN | PORT 1 | PORT 2 (not VIC20) |
DESCRIPTION |
---|---|---|---|
1 | JOY A0 | JOY B0 | ON |
2 | JOY A1 | JOY B1 | BELOW |
3 | JOY A2 | JOY B2 | LEFT |
4 | JOY A3 | JOY B3 | RIGHT |
5 | POT AY | POT BY | INPUT Y |
6 | PULS. TO | PULS. B. | FIRE |
7 | +5 VOLT | +5 VOLT | 100mA MAX |
8 | GND | GND | |
9 | POT AX | POT BX | INPUT X |
PIN | PORT 1 | PORT 2 | DESCRIPTION |
---|---|---|---|
1 | JOY A0 | JOY B0 | ON |
2 | JOY A1 | JOY B1 | BELOW |
3 | JOY A2 | JOY B2 | LEFT |
4 | JOY A3 | JOY B3 | RIGHT |
5 | +5V DC | +5V DC | |
6 | PULS. TO | PULS. B. | FIRE |
7 | GND | GND | |
8 | DATE 2 | DATE 1 | SELECT |
Pin | Signal | Direction (from C64) | Meaning |
---|---|---|---|
1 | GND | PWR extension | ground |
2-3 | +5V DC | PWR extension | +5V DC |
4 | _IRQ | In | InterruptRequest |
5 | R/_W | Out | Read or _Write indicator |
6 | DOT Clk | Out | Dot clock frequency |
7 | _IO1 | Out | Input/Output area 1 indicator |
8 | _GAME | In | Game configuration |
9 | _EXROM | In | External ROMs |
10 | _IO2 | Out | Input/Output area 2 indicators |
11 | _ROML | Out | ROM Low |
12 | B.A | Out | Bus Available |
13 | _DMA | In | Direct Memory Access |
14 | Q7 | I | Data lines 7 |
15 | Q6 | I | Data lines 6 |
16 | Q5 | I | Data lines 5 |
17 | Q4 | I | Datalines 4 |
18 | Q3 | I | Data lines 3 |
19 | Q2 | I | Data lines 2 |
20 | Q1 | I | Data line 1 |
21 | D0 | I | Dataline 0 |
22-A | GND | PWR extension | ground |
b | _ROMH | Out | ROM High |
c | _RESET | In | Reset |
D. | _NMI | In | Non-maskable interrupts |
And | PHI2 | Out | Phase 2 clock |
F. | A15 | Out | Address line 15 |
H. | A14 | Out | Address line 14 |
j | A13 | Out | Address line 13 |
k | A12 | Out | Address line 12 |
L | A11 | Out | Address line 11 |
m | A10 | Out | Address line 10 |
No | A9 | Out | Address line 9 |
P. | A8 | Out | Address line 8 |
R | A7 | Out | Address line 7 |
S. | A6 | Out | Address line 6 |
T | A5 | Out | Address line 5 |
u | A4 | Out | Address line 4 |
v | A3 | Out | Address line 3 |
w | A2 | Out | Address line 2 |
x | A1 | Out | Address line 1 |
Y | A0 | Out | Address line 0 |
Z | GND | PWR extension | ground |
Pin | signal | Description | Comment |
---|---|---|---|
1 | GND | ground | (0 Volts) |
2 | D0 | data line 0 | databus of the computer |
3 | Q1 | data line 1 | |
4 | Q2 | data lines 2 | |
5 | Q3 | data lines 3 | |
6 | Q4 | data lines 4 | |
7 | Q5 | data lines 5 | |
8 | Q6 | dataline 6 | |
9 | Q7 | data lines 7 | |
10 | /BLK 1 | Memory block 1 | Chip select for block 1; active-low, if address on bus is within $2000-$3FFF. |
11 | /BLK 2 | Memory block 2 | Chip select for block 2; active-low, if address on bus is within $4000-$5FFF. |
12 | /BLK 3 | Memory block 3 | Chip select for block 3; active-low, if address on bus is within $6000-$7FFF. |
13 | /BLK 5 | Memory block 5 | Chip select for block 5; active-low, if address on bus is within $A000-$BFFF. |
14 | /RAM 1 | RAM 1 | Chip select for RAM (memory area $0400 – $07FF) |
15 | /RAM 2 | RAM 2 | Chip select for RAM (memory area $0800 – $0BFF) |
16 | /RAM 3 | RAM 3 | Chip select for RAM (memory area $0C00 – $0FFF) |
17 | VR/W | VIC Read – /Write | high during read cycle, low during write cycle of the VIC |
18 | CR/W | CPU Read-/Write | high during read cycle, low during write cycle of the CPU |
19 | /IRQ | InterruptRequest | Interrupt Request Line |
20 | NC | not connected | |
21 | +5V DC | Supply Voltage +5V DC | + 5 Volts DC. |
22 | GND | ground | (0 Volts) |
TO | GND | ground | (0 Volts) |
b | A0 | address line 0 | address bus of the computer |
c | A1 | address line 1 | |
D. | A2 | address line 2 | |
And | A3 | address line 3 | |
F. | A4 | address line 4 | |
H. | A5 | address line 5 | |
j | A6 | address line 6 | |
k | A7 | address line 7 | |
L | A8 | address line 8 | |
m | A9 | address line 9 | |
No | A10 | address line 10 | |
P. | A11 | address line 11 | |
R | A12 | address line 12 | |
S. | A13 | address line 13 | |
T | /I/O2 | inputs/outputs 2 | input/output area 2 ; active low, if address on the bus is within $9800-$9BFF. |
u | /I/O3 | inputs/outputs 3 | input/output area 3 ; active low, if address on the bus is within $9C00-$9FFF. |
v | SØ2 | S Phi 2 | system clock (1.108MHz for PAL, 1.018MHz for NTSC) |
w | /NMI | non-maskable interrupts | Non Maskable Interrupt Line |
x | /RESET | Reset | If you pull this line to low, all chips will be re-initialized. The program counter of the CPU will be loaded with the reset-vector $FFFC and $FFFD (usually $FFD22). |
Y | NC | not connected | |
Z | GND | ground | (0 Volts) |
PIN | SIGNAL | PIN | SIGNAL |
---|---|---|---|
1 | GND | TO | GND |
2 | +5V DC | b | C1 Low |
3 | +5V DC | c | _Reset |
4 | _IRQ | D. | RAS |
5 | R/_W | And | Ø0 |
6 | C1 High | F. | A15 |
7 | C2Low | H. | A14 |
8 | C2 High | j | A13 |
9 | _CS1 ($C000-$FFFF) | k | A12 |
10 | _CS0 ($8000-$BFFF) | L | A11 |
11 | CAS | m | A10 |
12 | Mux | No | A9 |
13 | B.A | P. | A8 |
14 | Q7 | R | A7 |
15 | Q6 | S. | A6 |
16 | Q5 | T | A5 |
17 | Q4 | u | A4 |
18 | Q3 | v | A3 |
19 | Q2 | w | A2 |
20 | Q1 | x | A1 |
21 | D0 | Y | A0 |
22 | AEC extension | Z | NC |
23 | Audio-in | YY | NC |
24 | Ø2 | BB | NC |
25 | GND | CC | GND |
Cookie | Durata | Descrizione |
---|---|---|
cookielawinfo-checkbox-analytics | 11 months | This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Analytics". |
cookielawinfo-checkbox-functional | 11 months | The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". |
cookielawinfo-checkbox-necessary | 11 months | This cookie is set by GDPR Cookie Consent plugin. The cookies is used to store the user consent for the cookies in the category "Necessary". |
cookielawinfo-checkbox-others | 11 months | This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Other. |
cookielawinfo-checkbox-performance | 11 months | This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Performance". |
viewed_cookie_policy | 11 months | The cookie is set by the GDPR Cookie Consent plugin and is used to store whether or not user has consented to the use of cookies. It does not store any personal data. |